[Avila] IXP4xx watchdog reset hang

[Jim Thompson]

I fought something similar a long, long time ago (on a power-pc based
platform, using Intel's StrataFlash, with u-boot (then called ppcboot)
when jffs2 was in-use as the root filesystem.

As David describes, the flash was being left in a state where it wasn't
in "read" mode on warm boot (which includes the reset due to your
watchdog timer) as well as when you type "reboot" (or equivalent).

(on cold boot the flash is set for read mode).

Try (re)-mounting the root filesystem (or all filesystems on the flash)
read-only, and then hitting the reset button and/or typing "shutdown -r".

If you get a clean re-boot, I'd start looking at how to get the flash
into a coherent state on the way down.  IMO, jffs2 should have code in
it to "clean up" its state on the way down (during reboot or panic)

Dealing with the watchdog needs to be handled ala the AN referenced.

Jim

loft wrote:

>David Holmer wrote:
>
>David,
>
>I don't know for sure that this is your problem, however we experienced,
>hunted and fixed this on the nslu2-linux effort. I'm also seeing it
>occasionally on a new Cirrus 93xx platform.  We saw this problem with
>the shutdown -r, where we knew the board was rebooting, but Redbot never
>ran.
>
>Cheers,
>
>Tom
>
>  
>
>>I've been working on getting the IXP4xx built in watchdog time operational
>>on our Avila boards. I've had partial success using the driver that comes in
>>the 2.6 kernel with the 0.6 release. The problem is that although the kernel
>>driver seems to setup the watchdog correctly, and the watchdog triggers a
>>reset at the right time (when it stops getting updates), the Avila board
>>only seems to reboot successfully some of the time. Often the board will
>>hang after the watchdog reset and I see no output on the serial port (i.e.
>>Redboot isn't coming up). Sometimes the watchdog works perfectly and the
>>system reboots normally.
>>
>>I did more investigation into the topic and I suspect I found the culprit.
>>It seems that the IXP4xx watchdog only triggers a local cpu-reset. The issue
>>seems to be if the flash isn't in read mode (e.g. write or erase modes) when
>>the watchdog triggers, then the cpu can't load the bootloader out of the
>>flash. Since we're using a JFFS2 file system, the flash could be in these
>>other states at any time.
>>
>>I found an Intel Application Note that seemed to have useful information:
>>"Intel StrataFlashR Memory to IntelR IXP42x Product Line of Network
>>Processors and IXC1100 Control Plane Processor Design Guide, Application
>>Note 785" at http://download.intel.com/design/flcomp/applnots/25378604.pdf
>>In section 4.5 "Reset Consideration" this app note seems to describe the
>>issues I'm experiencing and says that when interfacing StrataFlash with an
>>IXP42x the  PLL_LOCK pin on the IXP42x should by tied with some pulse width
>>extension circuitry to the RP# pin on the StrataFlash. 
>>
>>Do the Avila boards have this reset connection that Intel describes in the
>>App Note? If not is this something that is difficult to add to the PCB? Are
>>other people using the watchdog and experiencing this issue as well?
>>
>>- David Holmer
>>
>>
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>>
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